Senior Verification Engineer - Risc-V - (L355)

Exciting opportunity to work on the latest cutting-edge RISC-V technology in the semiconductor industry.

In this new role as a Senior Digital Verification Engineer, you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs and architecture.

I am looking to speak with digital verification engineers with 5+ years of experience - who have the following skills:

Required:Masters or PhD degree in Electronics / Microelectronics or similar field5+ years' experience in UVM environments & processASIC / FPGA developmentSystem Verilog for IP / SOC Verification of digital ICs / ASIC IP or chipsComplex ASIC designs & architecture for advanced technology nodesVerification Metrics definition, Coverage analysis and debugging skillsKnowledge and experience on setting up an ASIC Verification environment, methodology and flowvManager, vPlan and Regressions, etc.Digital Test Plan definition / creating / set-up test benchesScripting / coding skills - C / C++, Python, etc. Bonus skills:RISC-V / CPU / GPU (this is a bonus, not required)Knowledge of SOC verification is also a bonus Visa sponsorship can be offered if required (dependent on experience / qualifications).

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