Senior Verification Engineer - Risc-V

Job Opportunity: Senior Digital Verification Engineer
Exciting opportunity to work on the latest cutting edge RISC-V technology in the semiconductor industry. In this new role, you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs and architecture.
I am looking to speak with digital verification engineers with 5+ years of experience - who have the following skills:
Required Skills:

Masters or PhD degree in Electronics / Microelectronics or similar field
5+ years' experience in UVM environments & process ASIC / FPGA development
System Verilog for IP / SOC Verification of digital ICs / ASIC IP or chips
Complex ASIC designs & architecture for advanced technology nodes
Verification Metrics definition, Coverage analysis and debugging skills
Knowledge and experience on setting up an ASIC Verification environment, methodology and flow
Tools: vManager, vPlan and Regressions, etc.
Digital Test Plan definition / creating / set-up test benches
Scripting / coding skills - C/C++, Python, etc.

Bonus Skills:

Experience with RISC-V / CPU / GPU (this is a bonus, not required)
Knowledge of SOC verification is also a bonus

Note: Visa sponsorship can be offered if required (dependent on experience/qualifications)
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