Please note that candidates must have the right to live and work in the respective European country before applying. We are seeking a Junior Physical Digital Design Engineer to join our team of Design Engineers at one of our European offices. This role requires on-site presence with no remote option available. The candidate will be responsible for all aspects of physical design and implementation, actively contributing to the establishment of physical design methodologies and flow automation. As part of the design development team, you will focus on digital design implementation and verification of mixed-signal ICs using standard EDA tools. Essential Functions: Responsible for physical design, development, and verification of digital/mixed-signal ICs. Execute chip and block floorplan/implementation, power and clock distribution, chip assembly, Place & Route (P&R), Static Timing Analysis (STA), and Layout vs. Schematic (LVS)/Design Rule Check (DRC) to closure. Collaborate closely with the digital/analog design team for physical implementation and integration of custom analog blocks/interfaces/IPs. Qualifications: Advanced degree in Electrical Engineering, Computer Science, or equivalent. Preferred 1+ years of experience in Physical Digital Design. Preferred 2+ years of experience in ASIC design, verification, or related work. Strong written and verbal communication skills in English, with demonstrated ability to collaborate effectively in a team environment. Ability to work independently, follow design specifications, and execute tasks to meet project milestones with high quality. Solid knowledge of the ASIC development process and digital design techniques. Experience with programming, scripting, and automation languages like Perl, TCL, Unix, or Python. Technical proficiency in: Verilog/System Verilog coding. Synthesis, Clock Tree Synthesis (CTS), Design for Testability (DFT), Extraction, and STA closure across multiple process corners. Multipower domain, signal integrity, and power/IR drop analysis. Linting and Clock Domain Crossing (CDC) requirements. Functional and timing ECO methodologies, both manual and tool-driven. Physical Design Verification methodologies to debug LVS/DRC issues at chip/block level. Familiarity with industry-standard physical design tools, preferably Cadence Encounter/Innovus or Synopsys ICC/ICC2. Desired experience includes physical SOC design involving microcontroller (uC) design (ARM/RISCV), knowledge of power management applications, familiarity with I/F protocols (I2C, SPI, USB, PMBUS, etc.). This role can be based at any of the following office locations: Barcelona, Spain Enschede/Nijmegen, Netherlands Porto/Lisbon, Portugal
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