Job Reference: 780_24_CS_V_RE1
Position: Research Engineer - Verification for RISC-V cores and accelerators (RE1)
Closing Date: Saturday, 16 November, 2024
About BSC: The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain.
It houses Mare Nostrum, one of the most powerful supercomputers in Europe, and is now hosting entity for Euro HPC JU, leading large-scale investments and HPC provision in Europe.
The mission of BSC is to research, develop, and manage information technologies to facilitate scientific progress.
BSC combines HPC service provision and R&D into both computer and computational science under one roof, currently having over 1000 staff from 60 countries.
We are particularly interested in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research.
In instances of equal merit, the incorporation of the under-represented sex will be favoured.
We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.
Context And Mission: BSC is constructing a full RISC-V ecosystem, from the design of the processors to the tape-out of them; also, BSC is working on the full software stack.
This vacancy is for a junior verification engineer to work on the verification for this processor and accelerator.
Key Duties: Verify complex digital designs, focused on vector units and other accelerators. Collaborate closely with design and verification engineers in active projects and perform hands-on verification. Build efficient and effective verification environments using UVM, System Verilog to exercise processor designs through their corner-cases and expose all types of bugs. Involved in the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, and coverage definition. Requirements: Education: BS or MS degree in Electrical Engineering, Computer Engineering, or equivalent. Essential Knowledge and Professional Experience: Experience using Universal Verification Methodology (UVM), simulating, debugging, and documenting results. Knowledge of and experience with industry-standard simulators (Model/Questa Sim, VCS, etc.
), revision control systems, and regression systems. Experienced in several key DV methodologies: UVM, System Verilog Assertions, functional coverage, Assembly/C-based random/constrained-random Verification, Formal Verification, Verification IPs. Strong debugging skills and able to work with design engineers to deliver functionally correct design blocks. Scripting experience using languages like Python, Perl, Bash, or Tcl.
Familiarity with Linux. Excellent interpersonal, written, and verbal communication skills. Fluency in English is essential; Spanish is welcome. Additional Knowledge and Professional Experience: Deep understanding of Modern in-order and out-of-order processor core microarchitecture and accelerator designs. Experience with one or more Instruction Set Architectures (ISAs) including RISC-V. Experience with vector architectures, particularly implementing the RISC-V V-extension. Competences: Effective communicator, multitasker, and collaborative worker. Ability to think creatively and work independently. Ability to take initiative, prioritize, and work under set deadlines. Conditions: Full-time contract (37.5h/week) with a good working environment and flexible working hours. Open-ended contract due to technical and scientific activities linked to the project. 23 paid vacation days plus 24th and 31st of December. Competitive salary commensurate with qualifications and experience. Starting date: 27/11/2023. Applications procedure and process: All applications must be made through the BSC website and contain:
A full CV in English including contact details. A Cover Letter with a statement of interest in English, including two contacts for further references. Applications without these documents will not be considered.
The recruitment process follows OTM-R principles, ensuring a gender-balanced recruitment panel.
Deadline: The vacancy will remain open until a suitable candidate has been hired.
Applications will be regularly reviewed.
BSC-CNS is an equal opportunity employer committed to diversity and inclusion.
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