Digital Design Engineer - (Ph-942)

Digital Design Engineer
Location: Munich (Fully Remote - anywhere in EU)
Term: contract until end of year + extensions.
Rate: Negotiable
ResponsibilitiesAdapt design (i.e. VHDL code) for different IPsRun logic synthesis, adapt timing constraints and make sure the required timing requirements are metOwn and create design-related documentation to comply with relevant standards for safety (ISO 26262) and security (ISO 21434)Perform design quality checks by synthesis, structural checks (e.g. lint, CDC, RDC), design for testability, power analysis, etc.Provide relevant reports to show progressDeliverables and ResultsSynthesizable RTL code, delivered into the configuration management systemQuality check reports and KPI reportsSafety analysis and derived work productsDocumentation of design implementationRequirementsSenior experience in VHDL, Spyglass, VerilogProven working experience in area and power-efficient RTL design (VHDL or Verilog) with a natural understanding of how RTL will map to gate-level structuresProven ability to work in a team to undertake a larger design projectWorking experience in international and cross-functional technical teams within a multi-cultural environmentTools: Xcelium, Spyglass, DesignCompiler / FusionCompiler, LEC, ATPG, System Verilog, VHDL, basic knowledge of scripting languages - perl / python
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