Job Reference964_24_CS_V_RE2-3
PositionVerification engineer for system level - DARE (RE2-3)
Closing DateFriday, 31 January, 2025
About BSC The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science under one roof, and currently has over 1000 staff from 60 countries.
We are particularly interested in the strengths and lived experiences of women and underrepresented groups to help us avoid perpetuating biases and oversights in science and IT research. In instances of equal merit, the incorporation of the under-represented sex will be favoured. We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.
If you consider that you do not meet all the requirements, we encourage you to continue applying for the job offer. We value diversity of experiences and skills, and you could bring unique perspectives to our team.
Context And Mission BSC is looking for talented and motivated professionals with expertise in Design Verification for a chip integrating a European HPC accelerator in the context of the DARE Project and other related research projects. The design is based on RISC-V architecture. BSC contributes a RISC-V vector accelerator to the EPI project and verifying the functional correctness of the chip is key for success.
Key Duties You will use your design and verification expertise to verify complex RISC-V digital designs, focused on a system that integrates vector units and scalar processors, and possibly other accelerators.You will collaborate closely with design and verification engineers in active projects and perform hands-on verification.Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments.You will be responsible for the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.You will automatize the processes by creating and maintaining verification & post-processing scripts.You will train others in the configuration, deployment, use and/or maintenance of verification software, scripts and workflows.You supervise, guide and coordinate the work of less experienced Verification engineers.You will define and implement coverage plans for the design, and analyse the code and functional coverage results.Requirements EducationBS degree in Electrical Engineering, Computer Engineering, or equivalent.Essential Knowledge and Professional ExperienceExperience with the full verification life cycle from test planning to sign-off.Working knowledge of Universal Verification Methodology (UVM), writing test plans, simulating, debugging, and documenting results.Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.).Experience in key DV methodologies: UVM, cosimulation, SystemVerilog Assertions, functional coverage, Verification IPs.Strong debugging and triaging skills and ability to work with design engineers.Strong scripting experience using languages like Python, Perl, Bash or Tcl.Experience in the implementation of SystemVerilog UVM testbenches for a complex digital design.Excellent interpersonal, written, and verbal communication skills.Ability to work as part of a cross-functional team according to an established timeline.Additional Knowledge and Professional ExperienceDeep understanding of Modern in-order and out-of-order processor core and accelerator designs.Experience with one or more Instruction Set Architectures (ISAs) including RISC-V.Good knowledge of common protocols and interfaces such as AXI, SPI, JTAG or UART.Fluency in English is essential, Spanish is welcome.CompetencesThe candidate must be an effective communicator, multitask, and work well on collaborative designs.Ability to think creatively and work independently.Conditions The position will be located at BSC within the Computer Sciences Department.We offer a full-time contract (37.5h/week), a good working environment, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures.Duration: Open-ended contract due to technical and scientific activities linked to the project.Holidays: 23 paid vacation days plus 24th and 31st of December.Salary: competitive salary commensurate with qualifications and experience.Starting date: asap.Applications procedure and process All applications must be submitted via the BSC website and contain:
A full CV in English, including contact details.A cover/motivation letter with a statement of interest in English.Development of the recruitment process The selection will be carried out through a competitive examination system. The recruitment process consists of two phases:
Curriculum Analysis: Evaluation of previous experience and/or scientific history.Interview phase: The highest-rated candidates will be invited to the interview phase.The recruitment panel will be composed of at least three people, ensuring representation of women.
Deadline The vacancy will remain open until a suitable candidate has been hired.
OTM-R principles for selection processes BSC-CNS is committed to the principles of the Code of Conduct for the Recruitment of Researchers of the European Commission and the Open, Transparent and Merit-based Recruitment principles (OTM-R).
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