Validation Engineer

UVM(Verification Expert)Madrid, SpainPermanent(Onsite)Required Qualifications:• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.• Experience: o 10+ years of experience in UVM-based verification for digital IC/ASIC/SoC designs.o Hands-on experience with simulation tools like Cadence Xcelium, Mentor Graphics Questa, Synopsys VCS, or similar.o Proficiency in SystemVerilog for verification, including the development of complex UVM components and test environments.o Experience with writing SystemVerilog Assertions (SVA) and using assertion-based verification.o Proven ability to create, maintain, and execute regression test suites for large-scale digital designs.