.Our client, a leading global IT service provider, is recruiting an UVM Development Engineer (Verification Expert) to join their project in Spain.Position Title: UVM Development Engineer (Verification Expert) Position Type: Permanent Start Date: ASAP Location: Madrid, Spain - no remote work Contact: Davor Molnar | +49 (0) 89 23 88 98 63 We are seeking an experienced UVM (Universal Verification Methodology) Development Engineer with expertise in simulation tools like Cadence Xcelium (or similar), to join our verification team.The ideal candidate will have a strong background in creating complex verification environments using UVM and driving the verification of digital designs through simulation.This role is critical in ensuring the functionality, performance, and reliability of ASIC/So C and FPGA designs in cutting-edge projects.Responsibilities: UVM Testbench Development: Develop UVM-based testbench to verify digital designs (ASICs, So Cs, or FPGAs) at the block, subsystem, and system levels.Architect, design, and implement reusable verification components such as drivers, monitors, scoreboards, and sequences.Create constrained-random test environments, functional coverage models, and assertions to ensure comprehensive verification.Simulation and Debugging: Use simulation tools such as Cadence Xcelium, Mentor Graphics Questa, Synopsys VCS, or similar for running simulations and debugging complex designs.Analyze waveforms, logs, and results to pinpoint issues and resolve design or verification- related bugs.Conduct regression testing, performance analysis, and ensure test coverage goals are met.Implement code and functional coverage, track metrics, and improve coverage closure.Verification Planning and Execution: Develop detailed verification plans based on design specifications, functional requirements, and target coverage metrics.Collaborate with design teams to understand the design architecture and define verification strategies.Execute test cases for various configurations and modes of the design, ensuring adherence to verification goals and milestones.UVM Methodology Expertise: Ensure the use of best practices for UVM development, including adherence to coding standards, object-oriented programming principles, and modularity.Optimize UVM testbench components for performance, reusability, and scalability.Mentor junior verification engineers on UVM methodology and best practices, providing guidance on code reviews, debugging, and problem-solving.Automation and Scripting: Develop automation scripts for simulation, regression runs, and reporting using scripting languages such as Python, Perl, or Tcl.Implement makefiles, run scripts, and automation flows to streamline the verification process and maximize efficiency.Assertion-Based Verification (ABV): Leverage assertion-based verification techniques to capture critical design behaviors and ensure proper functionality