(UK342) - Senior Digital Communications Design Engineer (M/F)Location: Madrid Tres Cantos, Spain
Thales people architect and deliver satellite-based systems that help position, connect and observe our planet, and push the boundaries of our understanding of planet's resources. Our systems are in orbit at 400 km, 20000 km, 36000 km and beyond to the edges of the solar system. Thales in Spain is a leader in technological solutions applied to Defence, Aeronautics, Security, Transportation and Space.
At Thales Alenia Space in Spain, we are looking for a Senior Digital Communications Design Engineer to join our Radiofrequency Equipment Department!
Responsibilities:Evaluate the customer specification and perform the flow-down of these requirements (up/down conversions, digital filtering, modulation/demodulation, coding/decoding, NCO, interference mitigation) to VHDL specification.Generate the MATLAB/Simulink models of the processing blocks when needed to detail the VHDL requirements.Review the Design and Development of the FPGA.Participate in the FW-HW integration tests to ensure the correct implementation of the FPGA design with respect to the customer specification.Work closely with the VHDL designer's department and the technical responsible of the HW solution.Review the Validation Plan of the FPGA according to the FPGA requirements.Participate and lead the unit design reviews with customers in an international environment.About you:Bachelor's or Master's Degree in Engineering, Telecommunications, Electronics or similar.Experience of at least 5 years in the following areas:Leading electronic equipment design: Architecture trade-offs, selection of main components, frequency plan, RF line-up, noise & signal budgets, distortion budgets.Digital communication: modulation schemes, error correction coding, characterization of communication links.Digital Signal Processing Design for Up/Down conversions, digital filtering, modulation/demodulation, coding/decoding, NCO, interference mitigation.Specification and evaluation of FW processes and algorithms for FPGAs; debugging the FW-FPGA solution in the laboratory during HW-FW integration.Fluency in Spanish and English.Added value:Mentor Graphics, Momentum, HFSS, Labview, C/C++, VHDL.Experience in space sector: programs design rules and standards.Experience in Agile methodology.What do we offer?Smart Working (teleworking, flexible working time, equipment & tools endowment).Free meals at the office.28 vacation days.Pension plan.Individual training programs.Good working environment.We will consider being in possession of a certificate of disability.
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