.Staff Design Verification Engineer Apply locations: Spain, Valencia, Cortes Valencianas; Ireland, Cork Time type: Full time Posted on: Posted 30+ Days Ago Job requisition id: R243974 Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.
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The charter of ADI's CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions.
Today these technology areas include Capacitive Sensing, Optical Image Stabilization, PMIC, and Audio that drive growth in our portable and non-portable consumer business.
As part of our global operation and expanding business needs, we are now seeking to fill key roles in defining, developing, and verifying digital systems for this key market area.
This would scan the entire development cycle from concept phase, through design, verification, implementation, and release of products to customers.
The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products.
Responsibilities Based in ADD LOCATION OR LOCATIONS, this position will be responsible for contributing to: Verification of complex designs and sub-systems using leading edge verification methodologies.
Contribute and influence the decisions on methodologies/strategies to be adopted for the verification.
Strong knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
Architect the testbench and develop in UVM or Formal based verification approaches.
Proficient in developing unit and SoC level test benches using UVM.
Integrate the block testbench in chip-level UVM environment and verify integration.
Define test-plans, tests, and verification methodology for block/chip-level verification.
Work with the design team in generating test-plans and closure of code and functional coverage.
Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
Continuous interaction with analog co-sim and firmware team.
Managing scripts written in TCL/Perl/Python for different verification aspects.
Coding up in C tests on M3 Series Cortex based products