Senior Staff Digital Ic Design Verification Engineer

Responsibilities MaxLinear's team is growing and we are seeking a Senior Staff ASIC Verification Engineer. In this role, you will focus on the following:
Support ASIC verification development
Creation of block level and/or device test plans, testbench development, and testcase execution
Work closely with mixed signal teams for integration of high-speed analog behavioral models
Work closely with the design team to assist with pre-silicon debug
Provide documentation for test plans and testbenches
Assess functional code coverage reports and augment testcase to meet defined test goals
Prepare task list, effort estimate and commit to schedule
Qualifications Knowledge of verification languages: UVM, System-Verilog.
Knowledge of verification methodologies: testplan creation and execution, direct testcases, random testcases, formal testcases, coverage, etc.
Knowledge of verification at block level, cluster/subsystem level, top level.
Knowledge of scripting and programming using Perl or Python would be an asset
Experience with RTL design using Verilog and/or System Verilog
Experience with EDA tools for logic and gate level simulation
Strong logical and creative problem-solving skills with excellent analytical and debugging skills
Excellent written and good verbal English communication skills and teamwork
Bachelor or Master of Science
Compensation and Benefits Competitive Salary Package
Stock-based compensation
Private Medical Insurance
Life Insurance

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