Senior Staff Digital Ic Design Verification Engineer

Responsibilities MaxLinear's team is growing and we are seeking a Senior Staff ASIC Verification Engineer.
In this role, you will focus on the following:Support ASIC verification developmentCreation of block level and/or device test plans, testbench development, and testcase executionWork closely with mixed signal teams for integration of high-speed analog behavioral modelsWork closely with the design team to assist with pre-silicon debugProvide documentation for test plans and testbenchesAssess functional code coverage reports and augment testcase to meet defined test goalsPrepare task list, effort estimate and commit to scheduleQualifications Knowledge of verification languages: UVM, System-Verilog.Knowledge of verification methodologies: testplan creation and execution, direct testcases, random testcases, formal testcases, coverage, etc.Knowledge of verification at block level, cluster/subsystem level, top level.Knowledge of scripting and programming using Perl or Python would be an assetExperience with RTL design using Verilog and/or System VerilogExperience with EDA tools for logic and gate level simulationStrong logical and creative problem-solving skills with excellent analytical and debugging skillsExcellent written and good verbal English communication skills and teamworkBachelor or Master of ScienceCompensation and Benefits Competitive Salary PackageStock-based compensationPrivate Medical InsuranceLife Insurance#J-18808-Ljbffr