Senior Mixed Signal Verification Engineer

Senior Mixed Signal Verification EngineerResponsibilities:Develop accurate behavioral models for mixed-signal circuitsVerify the performance and accuracy of the developed models against circuit-level simulations and measurementsCollaborate closely with system architects and analog/digital designers to understand circuit specifications, design intent, and performance requirementsDevelop mixed signal verification strategies for state-of-the-art SoCs containing high speed digital circuits and sensitive analog/RF circuitsImplement verification plans and track their coverageDevelop and run system simulations to verify the design, analyze performance, power and timing, and uncover bugsReplicate root causes and debug issues in the pre-silicon environmentFind and implement corrective measures to resolve failing testsMaintain and improve existing functional verification infrastructure and methodologyImplement/maintain post processing scripts for assessing system performanceDevelop tools for automated generation of verification reports and regression managementQualifications:You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with at least 5 years of relevant experience in the industry.Experience in developing high quality validation plans, collecting and analyzing test results, and debugging failures to RTL/gate/schematic levelStrong problem-solving and teamwork skills, and strong verbal and written communication skillsAbility to produce results in a challenging, fast-paced, multi-site, multi-group environmentGood working knowledge of Verilog/SystemVerilog is a mustGood working knowledge of UVMGood working knowledge of DSP techniques used for assessing performance of Radar systemsExperience in setting up, running, and debugging Gate Level simulationsWork experience with at least one other verification aspect like System modeling, Formal verification, etc.
would be an added advantageProficiency in scripting languages and utilities including Make, Python, etc.
will be a bonusShould be able to contribute as an Individual Contributor or technically lead a group of team members as per requirements #J-18808-Ljbffr