Principal Verification Engineer - Team Lead

defaultResponsibilities:Verification of mixed-signal CMOS ICs and IP blocksDefine verification plans for mixed-signal circuits and ensure adequate verification coverage to enable bug-free silicon manufacturingModel analog and mixed-signal blocks using a high-level description language (e.G. SystemVerilog, VerilogAMS)Create DV (Design Verification) test cases, run associated simulations, and debug the resultsLead and mentor less experienced DV engineersPromote cutting-edge DV methodologies and make their use available to the communityMinimum Requirements:Successfully completed university degree in Electronics, Electrical Engineering, Physics, or comparableSeveral years (~7 years) of professional experience in mixed-signal design/verification with hands-on experience with relevant design/simulation toolsSolid knowledge of design verification methods, tools, and languages (Digital Mixed-Signal simulation, SystemVerilog, UVM, assertions ...)Experience in analog block modelingAnalytical mind to solve complex problems and debugging skillsTeam-oriented and ability to mentor less experienced engineersStrong commitment to deadlines and the advancement of the DV disciplineGood communication skills and proficiency in English#J-18808-Ljbffr