Principal Verification Engineer - Team Lead (D/M/F)

default Responsibilities: Verification of mixed-signal CMOS ICs and IP blocks Define verification plans for mixed-signal circuits and ensure adequate verification coverage to enable bug-free silicon manufacturing Model analog and mixed-signal blocks using a high-level description language (e.G.
SystemVerilog, VerilogAMS) Create DV (Design Verification) test cases, run associated simulations and debug the results Lead and mentor less experienced DV engineers Promote cutting-edge DV methodologies and make their use available to the community Minimum Requirements: Successfully completed university degree in Electronics, Electrical Engineering, Physics or comparable Several years (~7 years) of professional experience in mixed-signal design/verification with hands-on experience with relevant design/simulation tools Solid knowledge of design verification methods, tools and languages (Digital Mixed-Signal simulation, SystemVerilog, UVM, assertions …) Experience in analog block modeling Analytical mind to solve complex problems and debugging skills Team-oriented and ability to mentor less experienced engineers Strong commitment to deadlines and the advancement of the DV discipline Good communication skills and proficiency in English #J-18808-Ljbffr