Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.The Group:The charter of ADI's CSI team is to lead the market in a number of technology domains with highly differentiated sensing and signal processing solutions.
Today these technology areas include Capacitive Sensing, Optical Image Stabilization and Optical sensing which drive growth in our portable Consumer business.
With a goal to deliver sustainable growth the CSI group will present the successful candidate with a great opportunity for continuous career development as part of a highly motivated and supportive team.The Position:Analog Devices Valencia is looking for an enthusiastic physical design engineer for its Consumer Product development team.
The team is responsible for developing mixed signal subsystem for next generation consumer products.
The chips include digital signal processing data paths and embedded microprocessor systems combined with high precision analog subsystems.
This is an excellent opportunity to employ state-of-the-art design physical design methodologies, get exposure to a wide range of technical disciplines and career growth.
The job is available at our office in Valencia.Requirements:B.Tech/M.Tech.
in EE/ECE with 8+ years of experience in digital implementation.Strong knowledge in Floor planning, place and route, CTS, STA, ECO methodology, Power analysis and Physical design verification.Broad experience in synthesis and timing constraints.Experience with 40nm digital implementation is essential.Scripting skill and experience using languages such as Tcl, SKILL and Perl.Knowledge of the state of the art implementation tools.
Cadence tool experience preferred.Experience working with Perforce/ Methodics for versioning.Knowledge of CPF/UPF methodology is an added advantage.Knowledge of Cadence virtuoso tool is an advantage.Knowledge of foundry rules and ability to produce tape out ready GDS2 database is a plus.Technical ownership and hands on expertise needed.
Should be able to step in and take responsibility of implementation tasks when needed.Strong inter-personal, teamwork and communication skills are required.Responsibilities:Floorplan development, power/ground distribution, and clock distribution.Logic synthesis, cell placement, and interconnect routing.Equivalence-checking, timing closure, and physical verification (LVS, DRC).Strong collaboration with RTL designers to solve challenging problems.Own and deliver digital subsystems of significant size/complexity.Develop schedule and monitor progress.Effective teamwork involving engineers working in geographically disparate locations.Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days #J-18808-Ljbffr