.Principal Engineer, Design VerificationApplyLocations: United Kingdom, Edinburgh, SC, Freer; Spain, Valencia, CortesValencianas; United Kingdom, Newbury; Ireland, Cork; Ireland, LimerickTime Type: Full timePosted On: Posted 10 Days AgoJob Requisition ID: R243314Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY23 and approximately 26,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.Analog.Com and on LinkedIn and Twitter (X).The Group:The Custom Silicon Power (CSP) team is primarily focused on PMIC and hybrid Mixed-Signal / Power developments, for High-End / High-Volume electronic devices, such as Smartphones, Tablets, and Consumer Accessories.The Position:Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market.Complete verification ownership – Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure, and Code Coverage Closure.Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals.Actively explore and deploy techniques like Formal verification to achieve faster turnaround time on verification.Debug efficiently and clearly articulate gating issues to engineering leads.Integrate the block level testbench at SOC level and verify SOC integration.Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.Desired Qualifications & Experience:Electronic Engineering/Computer Engineering degree with 10+ years of progressive experience in Verification.Demonstrated experience in developing UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure, and assertion development.Strong understanding and experience of Verilog and System Verilog.Excellent debug and problem-solving skills.Experience with both IP and SOC level verification.Self-motivated, diligent, and has an eye for detail.Knowledge in AHB/AXI/APB/SPMI protocols is desirable; experience in Power aware simulations or Formal Verification is a big plus.Experience in Verilog-AMS, analog behavior modelling is desirable.Understanding of Buck-Boost/Inverse Buck-Boost, LDOs, BG reference concepts in the form of projects or coursework is a plus.Proficiency in scripting languages and utilities including Makefile, Python, Perl, etc.Good written and verbal communication skills.For positions requiring access to technical data, Analog Devices, Inc