The PhD student will work on a project framed in the use of integrable power systems for low-power applications.
In particular, the PhD student will work on the modelling with VERILOG-A of different sources of energy generation (triboelectric, piezoelectric, photovoltaic, RF) to include them in the design of integrated circuits for energy management.
The doctoral student will also characterize integrated circuits both by simulation and once manufactured.
The group to which the PhD student will join (COMMUNICATION INTEGRATED CIRCUITS) has more than 20 years of experience in the design of integrated circuits, especially for low power and very high frequency applications.
The group is composed of 6 doctors and 3 PhD students.
Tecnun, the Engineering School of the University of Navarra, offers a 3-year doctoral contract at its Technological Campus in San Sebastian (Spain).
Thesis should be completed in 3 years.
Working Schedule:7.75 hours per day.Flexible timetable: start between 8:00 and 9:30.Summer timetable: Only mornings starting June 15th and finishing August 31st (5.5 hours).Holidays:23 working days + Christmas holidays (24-Dec to 2-Jan).Requirements:Degree: Telecommunications Engineering or Electronics Engineer with a master's in Telecommunications, Embedded Systems, Electronic Design or similar.
Date of degree: 2022 or later (excluding Final Project).
Languages: Proficiency in English, Spanish desirable.
IT Knowledge: CADENCEVERILOGLABVIEW.Others: Experience in design and characterization of integrated circuits will be valued.Starting Date: Early 2025 (As soon as possible).
Documentation Required:Cover letter describing your motivation as a thesis candidate.Updated CV.Undergraduate and Master's degree transcripts.
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