.Descripción del puestoAbout OpenchipOpenchip is a European Silicon Engineering Company, headquartered in Barcelona, Spain. We aim to democratize the usage of Chips by developing Systems on Chip, SOCs, that combines RISC-V and accelerated chiplets for AI and HPC, everything interconnected with UCIe open interfaces. Our technologies will provide a value in multiple fields as Artificial Intelligence, Security and Privacy and Carbon Footprint Reduction. We are willing to change the Silicon Industry and help to build a more sustainable world, where collaboration and openness are by default. Our chips will be used in High Performance Computing, Autonomous Driving, Telecommunications, Personalized Medicine, Edge Computing and Cloud.We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.We can offer you an exciting and accelerated career path in a multicultural and multinational environment where innovation, teamwork and trust are in our DNA. You will have the opportunity to learn from senior professionals, use the most advanced technologies to develop chips and participate in one of the most relevant technological projects in the European Union.The Role:As a Junior Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.-Reading and analysing the system requirements and architecture requirement documents.Developing Verification environment development and maintenance in System Verilog/UVM/System C/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, ...).Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.Participation to verification methodology improvements.Qualifications:Master's degree in relevant field.Experience in relevant field of Verification of complex So C or IPExperience inSystem Verilog/UVMSystem C/C++Experience in Constrained random, Functional Coverage development, design debug.Experience in HW-SW co-verification and simulation