.The University of the Basque Country (UPV/EHU) SoC4sensing University-Business Chair presents an ambitious Research and Training Plan to develop microelectronics design skills in new generations of electronics engineers.The SoC4sensing chair is supported by 17 researchers from the APERT and GDED research groups in the UPV/EHU. It is co-funded by the Spanish Government and private sector companies such as IKERLAN Coop., System-on-Chip engineering S.L.. and the Basque Industry Association of Applied Knowledge and Technologies GAIA. This chair responds to the motivation of generating new economic activity based on new semiconductor devices that include differential elements for the industrial sectors of which there is a deep knowledge in the region.This thesis proposal will be developed in collaboration with IKERLAN research center. IKERLAN is currently launching a new research line on neuromorphic processing systems, covering both sensing and processing stages. Initial efforts will be aligned with the Horizon Europe NimbleAI project that brings together 19 leading academic and industry EU/UK partners under the coordination of IKERLAN. NimbleAI will leverage key principles of energy-efficient visual sensing and processing in biological eyes and brains and harness the latest advances in 3D stacked silicon integration, to create an integral sensing-processing architecture that efficiently and accurately runs computer vision algorithms in resource- and area-constrained endpoint chips.A unique collaborative framework to conduct a PhD that includes fully funded enrollment in a leading university in promoting this technology in the regional and national environment and close collaboration with a key high-tech research center. This ensures that the outcome of the thesis is both innovative and realistic in line with the current state of the technology, as well as applicable to real-world industry products in the short- to mid- term.Additionally, SoC4sensing Chair offers expert training on SoC VLSI design and funding for the tape-out of developed designs.We offer a flexible work model and a range of various training opportunities for personal growth.Your functions will be:This thesis is aimed at adapting an already developed DVS-based processing pipeline prototyped in FPGA for its implementation in silicon. The proposed pipeline includes DVS interface with foveation control, event-driven filter, event-to-frame conversion and frame delivery via AXI Stream interfaces and memory-mapped registers for access from a main CPU via AXI. Pioneering research lines will be explored within the framework of manufacturing this novel technology in silicon for the first time. Key areas of investigation may include:Power consumption optimization, such as analyzing advanced circuit design techniques for low power