Monolithic Power Systems (MPS) – Barcelona Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry.
We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures.
At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers.
Our portfolio of technology helps power our world --- come join our team and see how YOU can make a difference.
Job Description:Job Summary: A Digital Verification Engineer will work in the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.
Products to be designed/verified may include power management, signal management and mixed signal functions.
Essential Functions: UVM and System Verilog based Digital Verification environment definition and development.VIPs standardization, definition, development, and documentation.Define VIP's integration into the Project's Digital Verification environment.Digital Verification Metrics definition for RTL and Gate-Level Verification.Test Plan definition and development.Digital Verification Automation and Scripting.Regression's infrastructure definition, development, and management.Close interaction with Senior Digital and Analog Designers to develop VIP models.Review Digital Verification Metrics and Results of multiple projects.Define and design Digital Verification Top-Level Tests.Analyze and debug test results, code coverage, and functional coverage.Assist in digital verification estimation, planning, and scheduling to meet tape-out dates.Qualifications: PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.3+ years of strong experience in both RTL and Gate-Level Verification.Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.Knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.Excellent scripting and automation skills using Python and C/C++ (TCL is a plus).
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