Responsibilities MaxLinear's team is growing and we are seeking a Digital IC Design lead.As part of the R&D team developing cutting-edge communication systems, the candidate will either lead an ASIC digital design team or be an individual contributor.The position seeks highly-motivated individuals that enjoy working in a dynamic team environment, with a passion for solving challenging problems that can lead to high-impact advances in technology.Support ASIC SOC/IP design and development at various stages including from initial feasibility through to final device productionCreation of SOC/IP architecture and RTL for efficient power / area / performance design and implementationWork closely with mixed signal teams for integration of high-speed analog circuitsWork closely with the verification team on test plan and debug/fix failing test casesProvide documentation for functional description, implementation, operation, register descriptions, verification, and emulation test plansProvide synthesis constraints, timing closure and area optimizationsSupport various DFT methodologies and strategiesSupport pre-silicon emulation and fabricated device validation and lab debugPrepare task list, effort estimate and commit to scheduleWork closely with the SW team to bring up the digital blocks both in pre-silicon emulation and silicon validationQualifications Hands on experience with RTL design using Verilog and/or System VerilogHands on experience with Lint, CDC, code coverageUnderstanding on verification and test cases developmentExperience in some of the SOC architectures: top level, IP integration, CPUs, external interfaces (PCIe, serial, DDR/Flash), internal busses, NOCs, peripherals, clock/reset architecturesExperience in DSP designSystem knowledge in communications domain and its interface protocols is a plusKnowledge of scripting and programming using Perl, Python, tcl, for automation is a plusExperience with designing for low power, including power simulation and analysisExperience with high-speed digital design interfacing to Mixed Signal IP is a plusExperience in FPGA design or emulationPrototype lab bring-up and silicon validation experience would be an assetStrong logical and creative problem-solving skills with excellent analytical and debugging skillsExcellent written and good verbal English communication skills and teamworkExperience to work with cross functional and multi-site teamsExperience or wish to lead teams8-10 years of experience on ASIC designCompensation and Benefits Competitive Salary PackageStock-based compensationPrivate Medical InsuranceLife Insurance#J-18808-Ljbffr