Responsibilities MaxLinear's team is growing and we are seeking a Digital IC Design lead.
As part of the R&D team developing cutting-edge communication systems, the candidate will either lead an ASIC digital design team or be an individual contributor.
The position seeks highly-motivated individuals that enjoy working in a dynamic team environment, with a passion for solving challenging problems that can lead to high-impact advances in technology.
Support ASIC SOC/IP design and development at various stages including from initial feasibility through to final device production
Creation of SOC/IP architecture and RTL for efficient power / area / performance design and implementation
Work closely with mixed signal teams for integration of high-speed analog circuits
Work closely with the verification team on test plan and debug/fix failing test cases
Provide documentation for functional description, implementation, operation, register descriptions, verification, and emulation test plans
Provide synthesis constraints, timing closure and area optimizations
Support various DFT methodologies and strategies
Support pre-silicon emulation and fabricated device validation and lab debug
Prepare task list, effort estimate and commit to schedule
Work closely with the SW team to bring up the digital blocks both in pre-silicon emulation and silicon validation
Qualifications Hands on experience with RTL design using Verilog and/or System Verilog
Hands on experience with Lint, CDC, code coverage
Understanding on verification and test cases development
Experience in some of the SOC architectures: top level, IP integration, CPUs, external interfaces (PCIe, serial, DDR/Flash), internal busses, NOCs, peripherals, clock/reset architectures
Experience in DSP design
System knowledge in communications domain and its interface protocols is a plus
Knowledge of scripting and programming using Perl, Python, tcl, for automation is a plus
Experience with designing for low power, including power simulation and analysis
Experience with high-speed digital design interfacing to Mixed Signal IP is a plus
Experience in FPGA design or emulation
Prototype lab bring-up and silicon validation experience would be an asset
Strong logical and creative problem-solving skills with excellent analytical and debugging skills
Excellent written and good verbal English communication skills and teamwork
Experience to work with cross functional and multi-site teams
Experience or wish to lead teams
8-10 years of experience on ASIC design
Compensation and Benefits Competitive Salary Package
Stock-based compensation
Private Medical Insurance
Life Insurance
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