Digital Design Engineer - (Ph-942)

Digital Design Engineer Location: Munich (Fully Remote - anywhere in EU) Term: contract until end of year + extensions.
Rate: Negotiable Responsibilities Adapt design (i.e.
VHDL code) for different IPs Run logic synthesis, adapt timing constraints and make sure the required timing requirements are met Own and create design-related documentation to comply with relevant standards for safety (ISO 26262) and security (ISO 21434) Perform design quality checks by synthesis, structural checks (e.g.
lint, CDC, RDC), design for testability, power analysis, etc.
Provide relevant reports to show progress Deliverables and Results Synthesizable RTL code, delivered into the configuration management system Quality check reports and KPI reports Safety analysis and derived work products Documentation of design implementation Requirements Senior experience in VHDL, Spyglass, Verilog Proven working experience in area and power-efficient RTL design (VHDL or Verilog) with a natural understanding of how RTL will map to gate-level structures Proven ability to work in a team to undertake a larger design project Working experience in international and cross-functional technical teams within a multi-cultural environment Tools: Xcelium, Spyglass, DesignCompiler / FusionCompiler, LEC, ATPG, System Verilog, VHDL, basic knowledge of scripting languages - perl / python #J-18808-Ljbffr